JT6N46S 2000-07-21 1/7 toshiba cmos integrated circuit silicon monolithic j t 6 n 4 6 s single-chip system lsi for rfid card the JT6N46S is a system lsi for radio frequency identification (rfid) wireless cards. the JT6N46S incorporates an analog circuit, a data processing circuit and data memory in a single chip. features ? high-noise-resistant psk modulation: binary phase-shift keying (bpsk) for both reader-to-rfid and rfid-to-reader transmission. ? start-stop synchronization and half-duplex transmission: with parity, 1 stop bit ? high-efficiency power generation circuit using electromagnetic induction: battery less operation, full-wave rectifier circuit, shunt regulator ? data processing logic circuit: digital pll, security circuit ? high-reliability e 2 prom: 4 kbits maximum write time: 7 ms (16-byte batch write) overwrite: 100,000 times data retention: 10 years ? selectable receive carrier frequency: 100 khz to 500 khz (when external antenna circuit is used) ? programmable security circuit: security level can be set ? high-speed transfer rate of 25 kbps: 1/16 of receive carrier frequency = 400 khz ? high-speed multi-read of 32 ids per second: when receive carrier frequency = 400 khz (id only read) ? supplied as chips or on wafer chip thickness: 175 m (typ.) ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of th e buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury o r damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in th e most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the products described in this document contain components made in the united states and subject to export control of the u.s. authorities. diversion contrary to the u.s. law is prohibited. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707eda1
JT6N46S 2000-07-21 2/7 system block diagram rectifier circuit ant1 ant2 e 2 prom (1 kbit) data processing, security and multi-read functions modulator demodulator digital pll voltage detector bgr shunt regulator v dd 0.1 f (recommended value) transmission circuit carrier extraction circuit transmission control osc gnd v dd
JT6N46S 2000-07-21 3/7 pad allocation pad coordinates pad no. pad name x-coordinate ( m) y-coordinate ( m) 1 test pin ? 1010 762 2 test pin ? 1010 622 3 test pin ? 1010 482 4 test pin ? 1010 342 5 test pin ? 1010 202 6 test pin ? 1010 62 7 test pin ? 1010 ? 78 8 test pin 226 ? 363 9 anapsk0 770 ? 802 10 ant1 1020 ? 466 11 ant2 1020 ? 326 12 v dd 1020 ? 186 13 gnd 1020 ? 46 note: values for x-and y-coordinates are pad center values. 1 2 3 4 5 6 7 0 y x 2.35 mm 1.92 mm 13 12 11 10 8 9 gnd v dd ant2 ant1
JT6N46S 2000-07-21 4/7 pin functions pin no. symbol function 10 ant1 rectifier diode input, antenna connection pin 1 11 ant2 rectifier diode input (carrier extraction input side), antenna connection pin 2 12 v dd power supply for bridge circuit output, regulator voltage and internal circuits 13 gnd gnd-internal circuit voltage reference 1~9 ? lsi test pins lsi external specifications parameter specifications power supply battery less-externally supplied by electromagnetic induction coupling type electromagnetic induction power feed frequency 100 khz~200 khz note: an antenna and a capacitor are connected externally. communications method receive: psk, transmission: psk (reply carrier frequency is half the receive carrier frequency) transfer speed 7.8 kbps (when receive carrier frequency is 125 khz) 1/16 of receive carrier frequency transfer method half-duplex start-stop synchronization transmission (with parity, 1 stop bit) memory size 1-kbit e 2 prom (256 bits are used as security area.) write time 7 ms max (for batch write of 8 bytes) control circuit key checking and access level control by hardware ? incorporates two access keys (6-byte key and 2-byte status). ? using access keys, read-only or write/read privilege can be set independently for each 32-byte area (programmable security). ? block write in units of 8 bytes and block read in units of 16 bytes using an access key and physical address. ? controls multi-read using multi-read command. multi-read 10 reads/s (power feed frequency of 125 khz when id only is read) operating temperature ? 20c~ + 85c
JT6N46S 2000-07-21 5/7 functions and specifications of the core block the JT6N46S is comprised of the following: an rf analog block for power generation, carrier extraction and regulation, and a digital block for data modulation, demodulation and data processing an e 2 prom for data storage. 1. analog block (1) rectifier circuit receives radio wave via the (external) antenna circuit and generates dc power for operating internal circuits with full-wave rectification. (2) shunt regulator maintains the voltage generated by the rectifier circuit at a fixed voltage, 3.1 v (typ.). the digital circuits and e 2 prom operate using the voltage supplied by the shunt regulator. the shunt regulator also protects internal circuits from the effects of strong electric fields. (3) carrier extraction circuit shapes the psk-processed received carrier in to a square wave which is then input to the logic circuits for demodulation. (4) oscillation circuit (osc) generates a clock for the digital pll in the logic block. (oscillation frequency range: 3 mhz~5 mhz) (5) transmission circuit (parallel transmitter circuit) modulates the reply using a resistance load from the ant1 side of the rectifier circuit. the reply carrier frequency is half the receive carrier frequency. at reply, the JT6N46S carries out modulation by halting all blocks except those needed for transmission and using all the power which would be dissipated by the halted blocks for reply. (6) voltage detector supports three types of voltage detector circuit for initializing the system and enabling/disabling e 2 prom writing. as a result, operation is always stable. 2. digital block (1) demodulator converts the psk signal shaped by the carrier extraction circuit of the analog block into binary data. (2) digital pll compares the frequency of the oscillator circuit in the analog block with the signal shaped by the carrier extraction circuit and generates a clock with a fixed frequency for operation of the entire digital block. using the clock the internal lsi operates in synchronize with the carrier. (3) data processing processes data according to the commands received. processes include parity check, e 2 prom write and read, and reset of the entire lsi. (4) security logic two keys can be set simultaneously using the security area allocated to the e 2 prom. using the keys, write/read, read or no access can be set in units of 32-byte blocks (obtained by dividing e 2 prom memory area by four). (for example, with key a, read/write for a particular block can be set, while with key b, read/write for any blocks can be set.) (5) status reply replies to a command from the r/w consist of the status followed by data. the status represents, the internal status of the lsi to the r/w. if the lsi status is normal, status data 00h is inserted at the beginning (without any parity, start or end bits) followed by the data. if the lsi status is abnormal, no data follows and only the status indicating the abnormality is sent. the bit corresponding to each abnormality condition which has occurred is set to 1 in the status field. (6) multi-read multi-read is a function used for reading multiple rfids in the communications area using the same reader/writer (r/w). an rfid (lsi) generates a random number internally using the multi-read command transmitted by the r/w. the rfid replies using the response timing determined by the corresponding time slot. thus, replies from the different rfids will not conflict, enabling data to be received properly by the r/w. note: depending on the reading environment, the ability to read all the data may fluctuate . in some cases, some data may be left unread (since it cannot be undetected). toshiba recommend the use of an additional chip with a detection function other than the multi-read function.
JT6N46S 2000-07-21 6/7 electrical characteristics 1. ratings parameter symbol operating rating unit input current (between ant1 gnd ant2) i ant dc40 ma operating temperature range t opr ? 20~+85 c storage temperature range t stg ? 50~+150 c * : unless otherwise specified, the specifications are within the above operating temperature range. 2. dc characteristics parameter symbol test circuit description min typ. max unit minimum operating voltage 1 v dd (min) ? minimum operating voltage excluding memory write (voltage check pin is v dd .) ? 2.0 2.2 v minimum operating voltage 2 v dd (eew) ? minimum operating voltage including memory write (voltage check pin is v dd .) ? 2.7 2.9 v operating current dissipation 1 i ddopr1 ? current dissipation for operations excluding memory write (v dd = 2.2 v) ? 350 450 a operating current dissipation 2 i ddopr2 ? current dissipation for all operations including memory write (v dd = 2.9 v) ? 400 500 a 3. operation characteristics parameter symbol test circuit description min typ. max unit receive carrier frequency f crr ? carrier frequency at which operation is possible 100 ? 200 khz reply carrier frequency f psk ? carrier frequency at reply fcrr 1/2 khz transfer rate ? ? transfer speed fcrr 1/16 bps receive 1-bit frequency ? ? receiving carrier frequency per bit 16 cycles reply 1-bit frequency ? ? reply carrier frequency per bit 8 cycles e 2 prom write time t pw ? ? ? ? 7 ms e 2 prom overwrite ted ? ? 10 5 ? ? no. of times e 2 prom data hold time pre ? ambient temperature: ? 20 c~ + 85 c 10 ? ? years
JT6N46S 2000-07-21 7/7 memory map page no. 8-byte block page no. 8-byte block 00h atr data 01h atr data 02h key 0010 03h key 0101 04h any data 05h any data 06h any data 07h any data 08h any data 09h any data 0ah any data 0bh any data 0ch any data 0dh any data 0eh any data 0fh any data note 1: atr: answer to reset. the lsi sends back the atr data after receiving a reset command or self reset. note 2: using the keys at 02h and 03h, access privileges can be set for the 32-byte blocks (enclosed by bold lines) from 04h to 1fh. note 3: read is performed in units of 16 bytes from even-numbered addresses, 00h, 02h 0eh. note 4: write to e 2 prom is performed in units of 8 bytes to addresses matching the page numbers above. the advantage of using this lsi is that it can be supplied as a single lsi for rfid allowing the user to configure peripherals (e.g. antennae, and reader/writers) so as to develop the desired system. however, because the peripheral environment may be highly user-specific, incompatibilities between the lsi and the user-configured environment (communications failures) may occur. please carry out sufficient research before using this lsi.
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